The fulfillment of Moore's law of an exponential growth of transistor density has been pushed to the limit within the past decade. Processing units have reached a turning point in their capability to scale in performance with increasing transistor densities. Contemporary processors ubiquitously follow the Von Neumann architecture – computation where data storage and computing function separately. Despite increased transistor densities, the ability to successfully transfer and communicate information between elements is limited by the transfer rate of connections - the von Neumann bottleneck. Development of highly interconnected devices provides a solution to this bottleneck by redistributing the information traffic into several branches thereby resolving the exchange between elements several times faster. However, this multithreading tactic suffers from limited fabrication techniques to resolve features in the sub-10 nm scale and increased noise with decreasing feature size. Here, we have developed a device using CMOS compatible technologies as a platform for hybrid-CMOS architectures and novel computation through a combination of controlled fabrication techniques with spontaneous nanowire formation. We propose the use of an atomic switch network (ASN) of interconnected Ag<sub>2</sub>S inorganic synapses with characteristics of a complex system ideal for maximal information transfer and memory storage.

Morphic atomic switch networks for beyond: Moore computing architectures

251st National Meeting (2016)

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