Many new applications such as autonomous driving, industrial automation and robotics and infrastructural facilities including smart electric grids require the direct combination of power electronics with control modules that are even capable of running artificial intelligence (AI) routines. These heterogeneous electronic systems provide the demanded new functionalities. At the same time, they must show high reliability and functional safety without exceeding the cost. Having various advantages such as small form factor, higher input/output density and high electrical/thermal performance, Low-Density Fan-Out (LDFO) (also called fan-out-wafer-level-packaging) technologies are getting significant attention for heterogeneous system integration. In this technology, reconstituted wafers with one or several dies per package site go through various fabrication steps such as molding, curing, debonding, redistribution layer processes, grinding, etc. The reconstituted wafers compile various materials with different thermal expansion and stiffness. Therefore, they warp when subjected to the temperature changes during these fabrication processes.

Warpage is a crucial challenge for the LDFO technology. Despite of many studies for minimizing the wafer warpage, excessive warpage occurs in certain wafer map configurations - often unexpectedly. It impedes the subsequent processes steps and results in reduced yield or even in a total loss of those wafers and dies. Analytical calculations used for designing these wafer maps are inadequate. They are based on linear material properties and uniform curvature assumptions, which do not reflect reality. Furthermore, they neglect the effects of gravity and the actual deformation behavior, which is manifold and nonlinear. Therefore, the systematic study is reported here to characterize the physics of wafer warpage.

The study focuses on the interactions between the silicon dies and the epoxy molding compound (EMC). The analytical models of the initial benchmark step consider both, 12’’ and 8’’ wafers. For the experiments, EMC/silicon bilayer wafers were industrially manufactured and processed to have different Si thicknesses. They are exposed to various thermal loading conditions. The newly developed measurement system featuring a 3-point support and an integrated heating and cooling chamber, which is designed for most uniform temperature distribution across the large, yet lightweight, wafers. For this, the airflow in the chamber had to be optimized carefully. As a result, the evolution of the wafer edge displacement could be studied precisely for different wafer thicknesses and various temperature changes.

Three displacement shapes have been obtained: i) linear spherical, ii) nonlinear spherical and iii) cylindrical. This complex characteristic has been analyzed - first for the simple bilayer structure and then for the reconstituted LDFO wafers. The study also included the viscoelastic characterization of the applied EMC materials by dynamic mechanical analysis (DMA) and thermomechanical analysis (TMA). The measured data was used in the numerical finite element (FE) analyses performed to understand the interrelated effects of coefficient of thermal expansion (CTE), glass transition temperature (Tg), and viscoelasticity of the EMCs on the wafer deformation.

A fully parametric FE model has been developed for EMC/Si bilayer and realistic reconstituted wafers to simulate the similar thermal cycles as performed in the experiments. The FE model has been validated by comparing the deformation results from the simulation with the measured warpage. Subsequently, the complex wafer deformation is analyzed thoroughly showing most interesting effect. When the temperature changes, most wafers reach a bifurcation point, beyond which warpage can be stable spherical or cylindrical shapes. Comparing both wafer sizes, 12" reach this bifurcation point earlier than 8’’ wafer. The FE analysis results have revealed the physical root cause and quantified the conditions.

Next, the systematic study was widened to the realistic reconstituted wafers. Interestingly, they also exhibit the bifurcation effect in the relevant ranges of design parameters such as die and mold thicknesses, die occupation rate and mold material. A sensitivity analysis quantified the parameters’ influences. This way, FE analysis has shown its capability to enable virtual prototyping. It provides good practical guidance to the optimal LDFO design, which avoids excessive warpage due to bifurcation. Hence, it directly increases the product yield and reliability.


The Systematic Study of Fan-Out Wafer Warpage Using Analytical, Numerical and Experimental Methods

Division / Sponsors: 
Electronic & Photonic Packaging Division (EPPD)

Paper Proceedings: https://asmedigitalcollection.asme.org/InterPACK/InterPACK2020/volume/84041

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