In recent years, power electronics technology is becoming more important than ever before and adequate thermal design and management of power electronics equipment are also becoming important from power efficiency, size and weight optimization standpoints. For motor drive application, switching devices such as MOS (Metal Oxide Semiconductor) transistor and IGBT (Insulated Gate Bipolar Transistor) are the key inverter components. Junction temperature prediction of these devices is vital for thermal design and management of motor drive systems. Especially, high speed temperature prediction methodologies are required because switching frequency of motor drive systems are kHz order and three dimensional simulation is not suitable from computational time and/or required computational resource standpoints.

As high speed temperature prediction methodology, one-dimensional simulation, such as thermal network methodology, is usually employed. In that case, package thermal resistance of switching devices is thought as constant and value under specific boundary conditions is applied to the simulation, without considering its influence on temperature prediction result.

Therefore, this paper investigates package thermal resistance of DPAK package, one of surface mount type semiconductor packages, employed for discrete power semiconductor devices, to establish new compact thermal model which ensures sufficient temperature prediction accuracy with lower computational load. Package thermal resistance is investigated through three-dimensional heat conduction simulation trials and real measurements in this paper.

Firstly, basic simulation cases only with DPAK package model are conducted by changing boundary conditions along DPAK package surface. It is found that package thermal resistance of DPAK package model varies by \~6.2℃/W drastically when boundary conditions are changed.

Secondly, simulation cases in which DPAK package is mounted on PCB (printed circuit board) are conducted to understand package thermal resistance under possible system implementation conditions. It is found that package thermal resistance of DPAK package is \~2.4 to 2.6 ℃/W with smallest copper patterns, while its value is \~1.1 to 1.2 ℃/W in the case that copper fully covers over PCB. Also, it is found that package thermal resistance and heat transfer rate ratio along heat spreader bottom can almost be modeled as linear function of thermal resistance related to body/heat spreader bottom temperature, respectively.

Thirdly, two types of PCB with different copper pattern size for DPAK package of n-channel MOS transistor device are prepared. Measurements are conducted to know package thermal resistance variation by copper pattern size. Transient thermal impedance curve is obtained from measurement result and is converted to a cumulative Rth-Cth curve to know and discuss the difference by copper pattern size of these two test boards. The difference is also discussed with and compared to that of simulation results.


Investigation Regarding Thermal Resistance of Surface Mount Type Discrete Power Semiconductor Package

Division / Sponsors: 
Electronic & Photonic Packaging Division (EPPD)

Paper Proceedings: https://asmedigitalcollection.asme.org/InterPACK/InterPACK2020/volume/84041

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