Electronics subjected to thermal cycling loads are prone to solder joint fatigue as a prevalent failure mechanism. Unavoidable differences in the coefficients of thermal expansion (CTE) between the printed circuit board (PCB) and electronic components yield thermo-mechanical stresses in these joints causing the fatigue during the operational life of the product. Knowledge about the degree of damage at a certain point of consumed life is a prerequisite of predictive measures w.r.t. maintenance on demand envisaged for a variety of electronics. To tackle the reliability issues especially in safety relevant electronic systems, physics of failure models of significant failure modes have been established in the past, based on experimental findings combined with the results of finite element analyses. The majority is dealing with solder joint fatigue under thermal cycling loading, being the primary cause of failure in the assemblies. In the frame of prognostics and health management (PHM) of electronics, expendable canary devices have therefore been introduced as early warning features of upcoming malfunction. With their ability to identify solder interconnect failures by accelerated degradation in comparison to the functional ones, they present an essential part of real-time prognostics addressing not only the statistical failure probabilities but individual components in the electronic system for estimation of the remaining useful product life. One way to achieve the acceleration of solder fatigue is to employ reduced solder pads for passives to fail in advance of regularly attached resistors as the target structures under identical loading conditions.

Using dedicated test boards, feasibility studies should prove the use of near-zero ohmic ceramic chip resistors with reduced solder pads as canary devices for prediction of failure in the interconnections to the PCB. Resistors with standard pad width were mounted in daisy chains for comparison. TC experiments and vibration tests as well as complementary FE simulations have been performed to investigate the time to failure of the canary and regular resistors, respectively. In addition, the test boards have been screwed on dedicated metal plates in order to investigate the influence of an application relevant mounting case by means of a 3^rd^ level reliability assessment. The paper will report on these studies in detail and give an outlook on the implementation of the canary structures in dual inverter boards for electrical powertrain applications. It will also discuss possible PHM features for power semiconductor devices.


Phm Features for Large Circuit Boards and Power Devices  for Electric Drivetrain Applications

Division / Sponsors: 
Electronic & Photonic Packaging Division (EPPD)

Paper Proceedings: https://asmedigitalcollection.asme.org/InterPACK/InterPACK2020/volume/84041

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