In the present generation, the internet with instant data transmission support increasing the demands for the high speed Ethernet. Development of 400G&nbsp;Ethernet is currently underway. There have two common coding schemes: non-return-to-zero (NRZ), and pulse-amplitude modulation 4-Level (PAM4). Because NRZ needs higher Nyquist frequency which results in higher channel dependent loss, PAM4 has become a main solution.In the data center and networking applications, high speed SerDes design are becoming so fast that signal integrity problems become more prominent. Whether using the non-return to zero (NRZ), or working the 4-level pulse amplitude modulation (PAM-4), substrate design challenges include the impedance discontinuities and the cross-talk. When there have an impedance discontinuity, there are bound to occur a reflection, which reduces the signal level seen at the receiver. Vias in the substrate are particularly important when designing the SerDes channel. Eliminating the impedance discontinuity requires accurate S-parameter extraction, because this need to correctly model of substrate layout in order to design appropriate impedance matching networks. And this will help minimize insertion loss. In addition to losses, SerDes channels designed to operate with fast rise times and high frequency signals, signals could excite noise, depending on the substrate design.In this paper, we use the 85 Ohm differential signal to investigate how to make better performance on the insertion loss, return loss, and cross-talk for the 112Gbps PAM4 application. The 12 layers substrate with low-loss dielectric ABF-GL102 is used. We discuss the void size of via land, which makes the impedance discontinuity and effect on signal integrity. Besides the void size, the density of ground core via also impacts the cross-talk between two pair signals. And bump/BGA arrangement are more deciding the cross-talk level.

Electrical Performances of Package Layout for High Speed Networking and Cloud Computing Application

Paper Proceedings: https://asmedigitalcollection.asme.org/InterPACK/InterPACK2021/volume/85505

ASME 2021 International Electronic Packaging Technical Conference and Exhibition (InterPACK2021)

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